1. Field of the Invention
The present invention relates to semiconductor packages, and, more particularly, to a carrier-free semiconductor package.
2. Description of Related Art
Conventionally, there are various kinds of semiconductor packages that use lead frames as chip carriers. For example, a QFN (Quad Flat Non-leaded) semiconductor package is a lead frame-based chip scale package, which is characterized in that the leads thereof do not extend out from the package sides as in a conventional quad flat package (QFP), thereby reducing the size of the semiconductor package.
However, due to the thickness of the encapsulant of the QFN package, the height of the QFN package cannot be further reduced to meet the demands for lighter, thinner and smaller semiconductor products. Therefore, carrier-free semiconductor packages have been developed, which are much lighter and thinner compared with conventional lead frame semiconductor packages.
FIG. 1 shows a carrier-free semiconductor package as disclosed by U.S. Pat. No. 5,830,800. Referring to FIG. 1, a plurality of conductive pads 14 are formed on a copper plate (not shown) by electroplating, and a semiconductor chip 16 having a plurality of electrode pads is disposed on the copper plate and electrically connected to the conductive pads 14 through a plurality of bonding wires 17. Further, a molding process is performed to form an encapsulant 18. Then, the copper plate is removed to expose the conductive pads 14. Subsequently, a solder mask layer 11 is formed to define positions of the conductive pads 14 so as for a plurality of solder balls 19 to be mounted on the conductive pads 14, respectively. As a result, a semiconductor package 1 is obtained. Related techniques are also disclosed in U.S. Pat. Nos. 6,770,959, 6,989,294, 6,933,594 and 6,872,661.
In the above-described semiconductor package, the number of conductive pads substantially corresponds to the number of the electrode pads of the semiconductor chip, such that the electrode pads can be electrically connected to the corresponding conductive pads, respectively. However, if a highly integrated chip is used, since the electrode pads of the chip are configured at a high density, a higher number of conductive pads are required, thus increasing the distance between the conductive pads and the chip and increasing the length of the wire loops of the bonding wires. Long bonding wires complicates the wire bonding process. Further, impacted by molding flow during the molding process, long bonding wires may easily sweep or shift so as to come into contact with each other, thereby easily short circuiting and adversely affecting the electrical connection quality of the semiconductor package. Furthermore, a long distance between the conductive pads and the semiconductor chip may complicate the wire bonding process and even cause failure of the wiring bonding process. In addition, long bonding wires increase material costs.
Accordingly, U.S. Pat. No. 7,638,879 discloses an RDL (redistribution layer) technique through which conductive pads can be extended to the periphery of a semiconductor chip so as to reduce the lengths or interlacing of bonding wires and reduce material costs. Referring to FIG. 2, a dielectric layer 21 is formed on a carrier 20 of copper through an attaching layer 200, and a plurality of openings 210 are formed in the dielectric layer 21 and filled with Ni/Au material 25. Then, a copper wiring layer 24 is formed on the dielectric layer 21 and the Ni/Au material 25 by electroplating. The wiring layer 24 has conductive pads 241 formed at ends thereof. Subsequently, a semiconductor chip 26 is disposed on the dielectric layer 21 and electrically connected to the conductive pads 241 through bonding wires 27. Then, an encapsulant 28 is formed to encapsulate the semiconductor chip 26 and the bonding wires 27. Finally, the carrier 20 and the attaching layer 200 are removed to expose the dielectric layer 21 and the Ni/Au material 25.
Further, a solder material (not shown) can be attached to the Ni/Au material 25 for connecting a circuit board (not shown). However, the electrical connecting and heat dissipating effects between the Ni/Au material 25 and the solder material are quite poor, which results in a low electrical connection quality for the semiconductor package.
Further, the carrier 20 of copper is quite expensive, thereby resulting in higher material costs.
Furthermore, when the semiconductor package 2 is disposed on a circuit board, a solder paste having a thickness of 0.1 mm must be formed on conductive pads of the circuit board first and then attached to the Ni/Au material 25. However, if warpage occurs to the semiconductor package 2, a too thin layer of solder paste prevents the Ni/Au material 25 from being reliably attached thereto, thus resulting in a poor electrical connection of the semiconductor package.
Therefore, there is a need to provide a carrier-free semiconductor package and a fabrication method thereof so as to overcome the above-described drawbacks.